ACTIVITY 4: Simulation of Semiconductor Fabrication Processes.

Under a privately funded project, research is under way at Cal State L.A. to develop a simulation software package to study copper deposition on a semiconductor wafer. The use of copper instead of aluminum to manufacture solid-state integrated circuits is a cutting edge technology that promises to increase the speed of future processors by many folds.

Currently, several major companies including IBM are engaged in copper research. The process of plating and polishing a wafer is a highly complex one, which involves multitudes of disciplines including mechanical, electrical and chemical processes. In its current state, often the optimal solution is sought through expensive and time-consuming trial and error process. Because of the complexity of the processes, simulation studies (which are norm in other industry) are not used.

In this activity we will study the manufacturing process of copper deposition on a semiconductor wafer and the salient factors affecting the uniformity and flatness of the copper deposit. We will develop simulation software creating a virtual deposition chamber where the designer can change various factors affecting the process simultaneously and be able to visually inspect the results and obtain quantitative information on various attributes on the wafer.