California State University, Los Angeles is a member of the Cadence University program. The Electrical and Computer Engineering courses that utilize the Cadence software tools are:
EE290-Electrical Engineering Computing
This course is focused on providing a thorough background on the software tools needed in Electrical Engineering as an integral part of the courses offered by the department. The course covers the use of computers in electrical engineering; hardware, software; languages; algorithms; structured design; spreadsheets; graphics; word processing; curve fitting; circuit simulation and other electrical engineering applications. PSPICE (professional version) is a fundamental part of the course material. As this course is required and taken before the Electrical Engineering core and electives, PSPICE has become a major platform from which to expand student usage. Various analysis types (e.g., DC, AC, Transient) are introduced to the students and subsequently used in other courses listed below.
EE211-Electric Circuits Lab, EE204-Electric Circuits-I, EE317-Electronics Lab, EE333-Circuit analysis II, EE336-Electronics, EE371-Analog Electronics, EE483-Power Electronics
These courses use various analysis tools of PSPICE as an integral part of the students learning experience, complementing the theory presented in the course. The laboratories provide a means of validating simulation results against actual measured circuit performances.
EE347-Computer Logic Design
This course covers integrated circuit digital functions; design of computer system by means of register transfer method; processor unit design; control logic design; and design of general purpose computers. The course utilizes the Verilog HDL simulation tool of Cadence.
EE439-Digital Integrated Circuits
The course provides an in-depth study of logic families aided by computer analysis; LSI and VLSI, circuit design; regenerative circuits; memories; and A-D converters. A variety of Cadence tools for VLSI layout of digital circuits and simulation are utilized in the course including the Virtuoso schematic and layout editors, DRC, LVS and extractor, PSPICE and HSPICE simulators.
EE448-HDL Design and Simulation Lab
The course covers the design of digital systems using a hardware description language (HDL). Hierarchical design methodologies are introduced, where designs can be modeled behaviorally and/or structurally. Designs are verified through simulation. The course utilizes the Verilog HDL simulation tool of Cadence.
The course covers central processor unit organization; microprocessor architecture; control unit organization; microprogramming; input-output, interface; and microcomputer hardware organization. The course utilizes the Verilog HDL simulation tool of Cadence.
The course covers system definitions and concepts; systems age; systems engineering process; conceptual, preliminary, and detail system design; system test and evaluation; systems engineering planning, organization, and management. The course utilizes the design for manufacturing and signal integrity tools.
EE566-System Analysis and Design
The course covers alternative system designs for decision making; models for economic evaluations; system optimization in design and operation; queuing systems; control concepts in system design; system design for reliability and affordability. The course utilizes the functional and formal verification and verification process automation tools.
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